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hm514400d series 4m fp dram (1-mword 4-bit) 1k refresh ade-203-679a (z) rev. 1.0 nov. 13, 1997 description the hitachi hm514400d is a cmos dynamic ram organized 1,048,576-word 4-bit. hm514400d has realized higher density, higher performance and various functions by employing 0.8 m m cmos process technology and some new cmos circuit design technologies. the hm514400d offers fast page mode as a high speed access mode. multiplexed address input permits the hm514400d to be packaged in standard 300-mil 26-pin plastic soj. features single 5 v ( 10%) access time: 60 ns/70 ns/80 ns (max) power dissipation ? active mode: 605 mw/550 mw/495 mw (max) ? standby mode: 11 mw (max) 0.55 mw (max) (l-version) fast page mode capability refresh cycles ? 1024 refresh cycles: 16 ms : 128 ms (l-version) 3 variations of refresh ? ras -only refresh ? cas -before- ras refresh ? hidden refresh test function battery backup operation (l-version)
hm514400d series 2 ordering information type no. access time package hm514400ds-6 hm514400ds-7 hm514400ds-8 60 ns 70 ns 80 ns 300-mil 26-pin plastic soj (cp-26/20d) hm514400dls-6 HM514400DLS-7 hm514400dls-8 60 ns 70 ns 80 ns
hm514400d series 3 pin arrangement 1 2 3 4 5 9 10 11 12 13 i/o1 i/o2 we ras a9 a0 a1 a2 a3 v cc v i/o4 i/o3 cas oe a8 a7 a6 a5 a4 ss 26 25 24 23 22 18 17 16 15 14 hm514400ds/dls series (top view) pin description pin name function a0 to a9 address input row address a0 to a9 column address a0 to a9 refresh address a0 to a9 i/o1 to i/o4 data-in/data-out ras row address strobe cas column address strobe we read/write enable oe output enable v cc power supply v ss ground
hm514400d series 4 block diagram 256 k memory array mat i/o bus & column decoder 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat i/o bus & column decoder i/o bus & column decoder i/o bus & column decoder 256 k memory array mat i/o bus & column decoder 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat i/o bus & column decoder i/o bus & column decoder i/o bus & column decoder row driver row driver row driver row driver row driver row driver row driver row driver row decoder & peripheral circuit we ras cas row driver row driver row driver row driver row driver row driver row driver row driver row address buffer column address buffer address a0?9 i/o4 buffer ras control circuit cas control circuit we control circuit oe oe control circuit i/o3 buffer i/o2 buffer i/o1 buffer i/o1 i/o2 i/o3 i/o4
hm514400d series 5 absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v t C1.0 to +7.0 v supply voltage relative to v ss v cc C1.0 to +7.0 v short circuit output current iout 50 ma power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg C55 to +125 c recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit note supply voltage v ss 0 00v v cc 4.5 5.0 5.5 v 1 input high voltage v ih 2.4 6.5 v 1 input low voltage v il C1.0 0.8 v 1 note: 1. all voltage referred to v ss . dc characteristics (ta = 0 to +70 c, v cc = 5 v 10%, v ss = 0 v) hm514400d -6 -7 -8 parameter symbol min ma x min ma x min ma x unit test conditions
hm514400d series 6 hm514400d -6 -7 -8 parameter symbol min ma x min ma x min ma x unit test conditions operating current *1, *2 i cc1 110 100 90 ma ras , cas cycling t rc = min standby current i cc2 2 2 2 ma ttl interface ras , cas = v ih dout = high-z 1 1 1 ma cmos interface ras , cas 3 v cc C 0.2 v dout = high-z standby current (l-version) *4 i cc2 100 100 100 m a cmos interface ras , cas =v ih we , oe , address and din = v ih or v il dout = high-z ras -only refresh current *2 i cc3 110 100 90 ma t rc = min standby current *1 i cc5 5 5 5 ma ras = v ih , cas = v il dout = enable cas -before- ras refresh current i cc6 110 100 90 ma t rc = min fast page mode current *1, *3 i cc7 110 100 90 ma t pc = min battery backup current *4 (standby with cbr refresh) (l-version) i cc10 200 200 200 m at rc = 125 m s t ras 1 m s we = v ih , cas = v il oe , address and din = v ih or v il dout = high-z input leakage current i li C10 10 C10 10 C10 10 m a 0 v vin 7 v output leakage current i lo C10 10 C10 10 C10 10 m a 0 v vout 7 v dout = disable output high voltage v oh 2.4 v cc 2.4 v cc 2.4 v cc v high iout = C5 ma output low voltage v ol 0 0.4 0 0.4 0 0.4 v low iout = 4.2 ma notes: 1. i cc depends on output load condition when the device is selected. i cc max is specified at the output open condition. 2. address can be changed twice or less while ras = v il . 3. address can be changed once or less while cas = v ih . 4. v cc C 0.2 v v ih 6.5 v and 0 v v il 0.2 v.
hm514400d series 7 capacitance (ta = 25 c, v cc = 5 v 10%) parameter symbol typ max unit notes input capacitance (address) c i1 5 pf 1 input capacitance (clocks) c i2 7 pf 1 output capacitance (data-in, data-out) c i/o 7 pf 1, 2 notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. cas = v ih to disable dout. ac characteristics (ta = 0 to +70 c, v cc = 5 v 10%, v ss = 0 v) *1, *14, *15, *16 test conditions input rise and fall time : 5 ns input timing reference levels : 0.8 v, 2.4 v output load : 2 ttl gate + c l (100 pf) (including scope and jig)
hm514400d series 8 read, write, read-modify-write and refresh cycles (common parameters) hm514400d -6 -7 -8 parameter symbol min max min max min max unit notes random read or write cycle time t rc 110 130 150 ns ras precharge time t rp 40 50 60 ns ras pulse width t ras 60 10000 70 10000 80 10000 ns 19 cas pulse width t cas 15 10000 20 10000 20 10000 ns 20 row address setup time t asr 0 0 0 ns row address hold time t rah 10 10 10 ns column address setup time t asc 0 0 0 ns column address hold time t cah 15 15 15 ns ras to cas delay time t rcd 20 45 20 50 20 60 ns 8 ras to column address delay time t rad 15 30 15 35 15 40 ns 9 ras hold time t rsh 15 20 20 ns cas hold time t csh 60 70 80 ns cas to ras precharge time t crp 10 10 10 ns oe to din delay time t odd 15 20 20 ns oe delay time from din t dzo 0 0 0 ns cas setup time from din t dzc 0 0 0 ns transition time (rise and fall) t t 350 350 350 ns7 refresh period t ref 16 16 16 ms refresh period (l-version) t ref 128 128 128 ms
hm514400d series 9 read cycle hm514400d -6 -7 -8 parameter symbol min max min max min max unit notes access time from ras t rac 60 70 80 ns 2, 3, 17 access time from cas t cac 15 20 20 ns 3, 4, 13, 17 access time from address t aa 30 35 40 ns 3, 5, 13, 17 access time from oe t oac 15 20 20 ns 3, 17 read command setup time t rcs 0 0 0 ns read command hold time to cas t rch 0 0 0 ns18 read command hold time to ras t rrh 0 0 0 ns18 column address to ras lead time t ral 30 35 40 ns output buffer turn-off time t off1 015 020 020 ns6 output buffer turn-off time to oe t off2 015 020 020 ns6 cas to din delay time t cdd 15 20 20 ns oe pulse width t oep 15 20 20 ns write cycle hm514400d -6 -7 -8 parameter symbol min max min max min max unit notes write command setup time t wcs 0 0 0 ns10 write command hold time t wch 15 15 15 ns write command pulse width t wp 10 10 10 ns write command to ras lead time t rwl 15 20 20 ns write command to cas lead time t cwl 15 20 20 ns data-in setup time t ds 0 0 0 ns11 data-in hold time t dh 15 15 15 ns 11
hm514400d series 10 read-modify-write cycle hm514400d -6 -7 -8 parameter symbol min max min max min max unit notes read-modify-write cycle time t rwc 150 180 200 ns ras to we delay time t rwd 80 95 105 ns 10 cas to we delay time t cwd 35 45 45 ns 10 column address to we delay time t awd 50 60 65 ns 10 oe hold time from we t oeh 15 20 20 ns refresh cycle hm514400d -6 -7 -8 parameter symbol min max min max min max unit notes cas setup time (cbr refresh cycle) t csr 10 10 10 ns cas hold time (cbr refresh cycle) t chr 10 10 10 ns ras precharge to cas hold time t rpc 10 10 10 ns cas precharge time in normal mode t cpn 10 10 10 ns fast page mode cycle hm514400d -6 -7 -8 parameter symbol min max min max min max unit notes fast page mode cycle time t pc 40 45 50 ns fast page mode cas precharge time t cp 10 10 10 ns fast page mode ras pulse width t rasc 100000 100000 100000 ns 12 access time from cas precharge t acp 35 40 45 ns 3, 13, 17 ras hold time from cas precharge t rhcp 35 40 45 ns
hm514400d series 11 fast page mode read-modify-write cycle hm514400d -6 -7 -8 parameter symbol min max min max min max unit notes fast page mode read-modify-write cycle time t pcm 80 95 100 ns fast page mode read-modify-write cycle cas precharge to we delay time t cpw 55 65 70 ns 10 test mode cycle hm514400d -6 -7 -8 parameter symbol min max min max min max unit notes
hm514400d series 12 hm514400d test mode we setup time t ws 0 0 0 ns test mode we hold time t wh 10 10 10 ns notes: 1. ac measurements assume t t = 5 ns. 2. assumes that t rcd t rcd (max) and t rad t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 3. measured with a load circuit equivalent to 2 ttl loads and 100 pf. 4. assumes that t rcd 3 t rcd (max) and t rad t rad (max). 5. assumes that t rcd t rcd (max) and t rad 3 t rad (max). 6. t off (max) defines the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih and v il . 8. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only, if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 9. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only, if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 10. t wcs , t rwd , t cwd , t cpw and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only; if t wcs 3 t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t rwd 3 t rwd (min), t cwd 3 t cwd (min), t cpw 3 t cpw (min) and t awd 3 t awd (min), the cycle is a read-modify- write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. these parameters are referred to cas leading edge in an early write cycle and to we leading edge in a delayed write or read-modify-write cycle. 12. t rasc defines ras pulse width in fast page mode cycles. 13. access time is determined by the longest among t aa , t cac and t acp . 14. an initial pause of 100 m s is required after power up followed by a minimum of eight initialization cycles ( ras -only refresh cycle or cas -before- ras refresh cycle). if the internal refresh counter is used, a minimum of eight cas -before- ras refresh cycles is required. 15. in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device.
hm514400d series 13 16. test mode operation specified in this data sheet is 2-bit test function controlled by control address bits - - - ca0. this test mode operation can be performed by we -and- cas -before- ras (wcbr) refresh cycle. refresh during test mode operation will be performed by normal read cycles or by wcbr refresh cycles. when the state of two test bits accord each other, the condition of the output data is high level. when the state of test bits do not accord, the condition of the output data is low level. in order to end this test mode operation, perform a ras -only refresh cycle or a cas -before- ras refresh cycle. 17. in a test mode read cycle, the value of t rac , t aa , t cac , t oac and t acp is delayed for 2 ns to 5ns for the specified value. these parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 18. either t rch or t rrh must be satisfied 19. t ras (min) = t rwd (min) + t rwl (min) + t t in read-modify-write cycle. 20. t cas (min) = t cwd (min) + t cwl (min) + t t in read-modify-write cycle. 21. xxx: h or l (h: v ih (min) v in v ih (max), l: v il (min) v in v il (max)) ///////: invalid dout when the address, clock and input pins are not described on timing waveforms, their pins must be applied v ih or v il .
hm514400d series 14 timing waveforms *21 read cycle ras cas address we dout oe din t rc t ras t rp t crp t rcd t rsh t cas t t t rad t ral t asc t cah t asr row column t rah t rcs t rch t rrh t dzc high-z dout t dzo t odd t rac t oep t aa t cac t off1 t csh t cdd t off2 t oac
hm514400d series 15 early write cycle ras cas address we din dout t rc t ras t rp t crp t csh t rcd t rsh t cas t t t asr t rah t asc t cah column row t wcs t wch t ds t dh din * t wcs wcs (min) high-z* t
hm514400d series 16 delayed write cycle * 15 address cas ras we din oe dout t rc t ras t rp t csh t rcd t rsh t cas t crp t t column row t asr t rah t asc t cah t rcs t cwl t rwl t wp t dzc t ds t dh t dzo t odd t oeh t off2 * high-z din invalid dout comes out, when oe is low level. invalid dout* *
hm514400d series 17 read-modify-write cycle * 15 address ras din dout oe we cas t rwc t ras t rp t crp t cas t rcd t t t rad t asr t rah t asc t cah column row t rcs t cwd t cwl t awd t rwd t rwl t wp t dzc t dh t ds din high-z t dzo t off2 t oeh t oep t cac t aa t oac t odd t rac dout
hm514400d series 18 ras -only refresh cycle cas ras address t rc t ras t rp t t t crp t rpc t crp t asr t rah row high-z dout
hm514400d series 19 cas -before- ras refresh cycle ras cas we address dout t rc t rp t ras t rp t rpc t t t cpn t csr t chr t cpn t rpc t crp t ws t wh t off1 high-z
hm514400d series 20 hidden refresh cycle din oe dout we address cas ras t rc t rc t rc t rp t ras t rp t ras t rp t ras t t t rcd t rsh t chr t crp t rad t ral t cah t asr t rah t asc t rcs cdd dzo t odd t t t cac t aa t rac t column row oac t high-z t cas rrh t rch t off1 t dzc t (read) (refresh) (refresh) off2 dout
hm514400d series 21 fast page mode read cycle we din oe dout address cas ras t rasc t rhcp t rp t t t csh t rcd t cas t cp t cas t pc t rsh t cp t cas t crp t ral t cah t asc t t asc t t rad t asr t rah t t rch t rch tt t rrh t rch t cdd high-z t dzc t cdd t dzc t cdd t high-z high-z t dzo t odd t dzo t odd t aa t aa t acp t t rac t aa t cac t cac t oac t cac t off1 dout dout dout row column cah cah rcs asc t rcs dzc acp t off1 t off1 t off2 t odd t oep t oac t off2 t oep t off2 t oep t oac t dzo rcs column column
hm514400d series 22 fast page mode early write cycle ras cas address we din dout t rasc t rp t t t csh t pc t rsh t crp t cas t cp t cas t cp t cas t rcd t asr t rah t asc t cah t asc t cah t asc t cah row t wcs t wcs t wcs t wch t wch t wch t ds t dh t ds t dh t ds t dh din din din high-z column column column * t wcs wcs (min) t
hm514400d series 23 fast page mode delayed write cycle * 15 din we address ras dout cas t rasc t rp t t t csh t pc t rsh t cas t rcd t cp t cas t cp t cas t crp t asr t rah t asc t t asc t cah t asc t cah row column t t rcs tt wp t cwl t cwl t t t t ds t t ds t dh din din din t rwl t rcs wp cah t rcs wp cwl dh ds dh oe t odd t oeh high-z column column
hm514400d series 24 fast page mode read-modify-write cycle * 15 din dout address ras t rasc t t cp t pcm t t t rcd t t cp t rad t asr t asc t t t rah t t cah t t cpw t t cpw t cwl t rwd t awd t awd t awd t cwd t t cwd t cwd t rcs t wp t t wp t ds t t dh t t ds t dzc t dh t odd t dh t cac t dzo t oeh t oeh t oeh t aa t t off2 din din din t rp t rwl t oac t odd t off2 t t odd t dzo t off2 t t t dzo aa t we cas oe dout dout dout t cah t ds column column column row rac cwl acp wp cwl t crp asc acp t asc rcs high-z high-z oac t dzc dzc rcs oac t cas t cas t cas aa t t oep t oep t oep cah cac cac high-z
hm514400d series 25 test mode cycle cbr or ras -only refresh ras cas we set cycle** test mode cycle *,** reset cycle normal mode ** * address, din, oe : h or l
hm514400d series 26 test mode set cycle we -and- cas -before ras -refresh cycle cas we address dout ras t rc t rp t ras t rp t chr t csr t rpc t rpc t crp t t t cpn t ws t wh t cpn t off1 high-z
hm514400d series 27 package dimensions hm514400ds/dls series (cp-26/20d) 16.90 17.27 max 0.74 7.62 0.13 8.51 0.13 26 14 1 13 0.10 5.08 0.43 0.10 3.50 0.26 + 0.21 ?0.24 2.40 1.30 max 59 22 18 0.80 +0.25 ?.17 1.27 hitachi code jedec eiaj weight (reference value) cp-26/20d conforms conforms 0.6 g 0.41 0.08 unit: mm dimension including the plating thickness base material dimension 6.79 + 0.19 ?0.18
hm514400d series 28 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi america, ltd. semiconductor & ic div. 2000 sierra point parkway brisbane, ca. 94005-1835 u s a tel: 415-589-8300 fax: 415-583-4207 hitachi europe gmbh continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30-00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 01628-585000 fax: 01628-585160 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071 copyright ?hitachi, ltd., 1997. all rights reserved. printed in japan.
hm514400d series 29 revision record rev. date contents of modification drawn by approved by 0.0 nov. 27, 1996 initial issue t. oono s.suzuki 1.0 nov. 13, 1997 deletion of hm514400dtt series

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